Introduction to RISC-V architecture Training Course
This course provides an introductory overview of the RISC-V architecture and the microcontrollers built upon it. Participants may optionally engage in practical exercises using the GD32VF103 microcontroller, involving programming with either the C language or assembly language via the RARS simulator.
This course is available as onsite live training in Serbia or online live training.Course Outline
Origins of the RISC-V architecture. Definition of its modular structure, including base architectures and extensions. Details on the RISC-V ISA, such as registers and the instruction set. Key features aligned with modern software concepts. A general overview of RISC-V implementations.
RISC-V system architecture. Handling exceptions. The CLIC interrupt controller. The ECLIC interrupt controller within the GD32VF103.
Practical Exercises:
1. Firmware development for the GD32VF103 using VS Code.
2. Working with GD32VF103 interrupts.
Requirements
Foundational knowledge of the C programming language.
Open Training Courses require 5+ participants.
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Testimonials (1)
Being able to ask for advanced subjects even if there were not planned initially.
Gabriel Chouinard - Spark Microsystems
Course - FreeRTOS: Programming for Real Time Operating Systems
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