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Course Outline

Origins of the RISC-V architecture. Definition of its modular structure, including base architectures and extensions. Details on the RISC-V ISA, such as registers and the instruction set. Key features aligned with modern software concepts. A general overview of RISC-V implementations.
RISC-V system architecture. Handling exceptions. The CLIC interrupt controller. The ECLIC interrupt controller within the GD32VF103.

Practical Exercises:
1. Firmware development for the GD32VF103 using VS Code.
2. Working with GD32VF103 interrupts.

Requirements

Foundational knowledge of the C programming language.

 7 Hours

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